6-117 march 1997 hm-6561/883 256 x 4 cmos ram features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? low power standby . . . . . . . . . . . . . . . . . . . . 50 m w max ? low power operation . . . . . . . . . . . . . 20mw/mhz max ? fast access time. . . . . . . . . . . . . . . . . . . . . . 200ns max ? data retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0v min ? ttl compatible input/output ? high output drive - 1 ttl load ? on-chip address registers ? common data in/out ? three-state output ? easy microprocessor interfacing description the hm-6561/883 is a 256 x 4 static cmos ram fabricated using self-aligned silicon gate technology. synchronous circuit design techniques are employed to achieve high per- formance and low power operation. on-chip latches are provided for address and data outputs allowing ef?cient interfacing with microprocessor systems. the data output buffers can be forced to a high impedance state for use in expanded memory arrays. the data inputs and outputs are multiplexed internally for common i/o bus compatibility. the hm-6561/883 is a fully static ram and may be maintained in any state for an inde?nite period of time. data retention supply voltage and supply current are guaranteed over temperature. ordering information pinout hm-6561/883 (cerdip) top view package temperature range 220ns 300ns pkg. no. cerdip -55 o c to +125 o c hm1-6561b/883 hm1-6561/883 f18.3 pin description a address input e chip enable w write enable s chip select dq data in/out 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 vcc w s1 dq3 dq2 dq1 dq0 a4 s2 a3 a2 a1 a0 a5 a6 gnd a7 e file number 2990.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
6-118 functional diagram notes: 1. all lines positive logic-active high. 2. three-state buffers: a high ? output active. 3. data latches: l high ? q = d and q latches on falling edge of l. 4. address latches and gated decoders: latch on falling edge of e and gate on falling edge of e. a a a4 a3 a2 latched address register gated column decoder and data i / o dq0 dq1 dq2 dq3 l gated row decoder 32 5 5 a a 32 x 32 matrix 8 8 8 8 g latch a q d l a latch a q d l a latch a q d l a latch a q d l a s1 s2 w e a0 a1 a5 a6 a7 g 33 l latched address register hm-6561/883
6-119 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input or output voltage. . . . . . . . . . . . . . . gnd -0.3v to vcc +0.3v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc cerdip package . . . . . . . . . . . . . . . . 74 o c/w 18 o c/w maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to +0.8v input high voltage . . . . . . . . . . . . . . . . . . . . . . . . vcc - 2.0v to vcc input rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns max table 1. hm-6561/883 dc electrical performance specifications device guaranteed and 100% tested parameter symbol (note 1) conditions group a subgroups temperature limits units min max output low voltage vol vcc = 4.5v, iol = 1.6ma 1, 2, 3 -55 o c t a +125 o c - 0.4 v output high voltage voh vcc = 4.5v, ioh = -0.4ma 1, 2, 3 -55 o c t a +125 o c 2.4 - v input leakage current ii vcc = 5.5v, vi = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -1.0 +1.0 m a input/output leakage current iioz vcc = 5.5v, vio = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -1.0 +1.0 m a data retention supply current iccdr vcc = 2.0v, e = vcc, io = 0ma, 1, 2, 3 -55 o c t a +125 o c- 10 m a operating supply current iccop vcc = 5.5v, (note 2), e = 1mhz, w = gnd, vi = vcc or gnd 1, 2, 3 -55 o c t a +125 o c- 4 ma standby supply current iccsb vcc = 5.5v, io = 0ma, vi = vcc or gnd 1, 2, 3 -55 o c t a +125 o c- 10 m a notes: 1. all voltages referenced to device gnd. 2. typical derating 1.5ma/mhz increase in iccop. hm-6561/883
6-120 table 2. hm-6561/883 a.c. electrical performance specifications device guaranteed and 100% tested parameter symbol (notes 1, 2) conditions group a sub- groups temperature limits units hm-6561b/883 hm-6561/883 min max min max chip enable access time (1) telqv vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c - 220 - 300 ns address access time (2) tavqv vcc = 4.5 and 5.5v, (note 3) 9, 10, 11 -55 o c t a +125 o c - 220 - 300 ns chip select output enable time (3) tslqx vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c5 - 5 - ns chip select output disable time (4) tshqz vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c - 120 - 150 ns chip enable pulse negative width (5) teleh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 220 - 300 - ns chip enable pulse positive width (6) tehel vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 100 - 100 - ns address setup time (7) tavel vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns address hold time (8) telax vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 40 - 50 - ns data setup time (9) tdvwh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 100 - 150 - ns data hold time (10) twhdx vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns write data delay time (11) twldv vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 20 - 30 - chip select write pulse setup time (12) twlsh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - 180 - ns chip enable write pulse setup time (13) twleh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - 180 - ns chip select write pulse hold time (14) tslwh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - 180 - ns chip enable write pulse hold time (15) telwh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - 180 - ns write enable pulse width (16) twlwh vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 120 - 180 - ns read or write cycle time (17) telel vcc = 4.5 and 5.5v 9, 10, 11 -55 o c t a +125 o c 320 - 400 - ns notes: 1. all voltages referenced to device gnd. 2. input pulse levels: 0.8v to vcc-2.0v; input rise and fall times: 5ns (max); input and output timing reference level: 1.5v; ou tput load: iol = 1.6ma, ioh = -0.4ma, cl = 50pf (min) - for cl greater than 50pf, access time is derated by 0.15ns per pf. 3. tavqv = telqv + tavel. hm-6561/883
6-121 test load circuit note: 1. test head capacitance includes stray and jig capacitance. table 3. hm-6561/883 electrical performance specifications symbol parameter conditions note temperature limits units min max ci input capacitance vcc = open, f = 1mhz, all measurements referenced to device ground 1t a = +25 o c-8pf co output capacitance vcc = open, f = 1mhz, all measurements referenced to device ground 1t a = +25 o c - 10 pf note: 1. the parameters listed in table 3 are controlled via design or process parameters are characterized upon initial design and af ter major process and/or design changes. table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100%/5004 1 final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a samples/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 groups c & d samples/5005 1, 7, 9 dut 1.5v iol ioh + - (note 1) cl equivalent circuit hm-6561/883
6-122 timing waveforms the hm-6561/883 read cycle is initiated on the falling edge of e. this signal latches the input address word into on-chip registers. minimum address setup and hold times must be met. after the required hold time, the address lines may change state without affecting device operation. in order to read the output data e, s1 and s2 must be low and w must be high. the output data will be valid at access time (telqv). the hm-6561/883 has output data latches that are con- trolled by e. on the rising edge of e the present data is latched and remains latched until e falls. either or both s1 or s2 may be used to force the output buffers into a high impedance state. (7) tavel (7) tavel (8) telax high high z previous data valid data latched high z (4) tshqz (4) tslqx (4) tshqz a e dq s1, s2 -1 time 01 2345 reference w valid (5) teleh (17) telel (6) tehel (6) tehel (1) telqv (2) tavqv figure 1. read cycle truth table time reference inputs output function e s1 wa dq -1 h h x x z memory disabled 0 x h v z cycle begins, addresses are latched 1 l l h x x output enabled 2 l l h x v output valid 3 l h x v output latched 4 h h x x z device disabled, prepare for next cycle (same as -1) 5 x h v z cycle ends, next cycle begins (same as 0) note: 1. device selected only if both s1 and s2 are low, and deselected if either s1 or s2 are high. hm-6561/883
6-123 timing waveforms (continued) the write cycle begins with the e falling edge latching the address. the write portion of the cycle is de?ned by e, s1, s2 and w all being low simultaneously. the write portion of the cycle is terminated by the ?rst rising edge of any control line, e, s1, s2 or w. the data setup and data hold times (tdvwh and twhdx) must be referenced to the terminat- ing signal. for example, if s2 rises ?rst, data setup and hold times become tdvs2h and ts2hdx; and are numerically equal to tdvwh and twhdx. data input/output multiplexing is controlled by w. care must be taken to avoid data bus con?icts, where the ram outputs become enabled when another device is driving the data inputs. the following two examples illustrate the timing required to avoid bus con?icts. case 1: both s1 and s2 fall before w falls. if both selects fall before w falls, the ram outputs will become enabled. w is used to disable the outputs, so a dis- able time (twlqz = twldv) must pass before any other device can begin to drive the data inputs. this method of operation requires a wider write pulse, because twldv + tdvwh is greater than twlwh. in this case twlsl + tshwh are meaningless and can be ignored. case 2: w falls before both s1 and s2 fall. if one or both selects are high until w falls, the outputs are guaranteed not to enable at the beginning of the cycle. this eliminates the concern for data bus con?icts and simpli?es data input timing. data input may be applied as early as convenient, and twldv is ignored. since w is not used to disable the outputs it can be shorter than in case 1; twlwh (7) tavel (8) valid (7) tavel telax next (11) twldv (10) twhdx valid data a e dq s1, s2 time w reference -1 0 1 2 3 4 5 (17) telel (5) teleh (6) tehel (6) tehel (13) twleh (15) telwh (16) twlwh (14) tslwh (12) twlsh figure 2. write cycle (9) tdvwh truth table time reference inputs function e s1 wa dq -1 h h x x x memory disabled 0 x x v x cycle begins, addresses are latched 1 l l l x x write period begins 2 l l x v data in is written 3 x h x x write is completed 4 h h x x x prepare for next cycle (same as -1) 5 x x v x cycle ends, next cycle begins (same as 0) note: 1. device selected only if both s1 and s2 are low, and deselected if either s1 or s2 are high. hm-6561/883
6-124 is the minimum write pulse. at the end of the write period, if w rises before either select the outputs will enable reading data just written. they will not disable until either select goes high (tshqz). if a series of consecutive write cycles are to be performed, w may remain low until all desired locations are written. this is an extension of case 2. read-modify-write cycles and read-write-read cycles can be performed (extension of case 1). in fact data may be modi?ed as many times as desired with e remaining low. burn-in circuit hm-6561/883 cerdip notes: all resistors 47k w 5%. f0 = 100khz 10%. f1 = f0 ? 2, f2 = f1 ? 2, f3 = f2 ? 2 . . . f12 = f11 ? 2. vcc = 5.5v 0.5v. vih = 4.5v 10%. vil = -0.2v to +0.4v. c1 = 0.01 m f min. if observe ignore case 1 both s1 and s2 = low before w = low twlqz twldv tdvwh twlwh case 2 w = low before both s1 and s2 = low twlwh tdvwh twlqz twldv 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 vcc w s1 dq3 dq2 dq1 dq0 a4 s2 a3 a2 a1 a0 a5 a6 gnd a7 e c1 vcc f6 f5 f4 f3 f8 f9 f10 f0 f7 f1 f0 f2 f2 f2 f2 f0 hm-6561/883
6-125 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 132 x 160 x 19 1mils metallization: type: si - al thickness: 11k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 1.337 x 10 5 a/cm 2 lead temperature (10s soldering): 300 o c metallization mask layout hm-6561/883 s1 dq3 dq2 dq1 dq0 s2 e gnd a7 a6 a5 a0 a1 a2 a3 vcc a4 w hm-6561/883
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